Dielectric absorption can be modeled as a parasitic ladder in parallel with an ideal capacitor as shown in FIG. 1 of the accompanying drawings. The equivalent circuit model 100 comprises ideal capacitor 102, parasitic resistor, Rp, 104, and parasitic capacitor, Cp, 106.
Prior art negative impedance converters, such as the circuit shown in FIG. 2, can reduce the effects of dielectric absorption. The prior art negative impedance converter 200 includes an operational amplifier (op amp) 202 having an impedance 204 fed back between its positive terminal 206 and its output port 208. The disadvantage associated with this type of negative impedance converter is that the input voltage is typically doubled at the output port. Another means of reducing dielectric absorption is to design circuits with low dielectric absorption capacitors, however, these tend to be physically large and costly.
In phase lock loop (PLL) circuits using filtering capacitors (also known as loop capacitors), dielectric absorption can cause existing lock times of 2-3 milliseconds (ms) to increase by as much as 50-100 percent. The effect of dielectric absorption in PLL circuits is primarily seen during a stepped voltage at the filter capacitor which corresponds to a stepped frequency. For example, a stepped voltage of a half volt at the filter capacitor can correspond to a stepped frequency of approximately 3 megahertz (MHz). When the operating frequency of the PLL is changed, the stepped frequency takes time to settle to the final desired operating frequency and this is referred to as the lock time of the PLL. The slow time constant of the parasitic resistor and parasitic capacitor associated with the filter capacitor's dielectric absorption prevents the PLL from settling quickly. For small frequency steps, typically steps of 2 MHz or less the effects of dielectric absorption are usually considered negligible. However, for large frequency steps, usually greater than 3 MHz, more charge has to be transferred to or from the parasitic capacitor causing the lock time to be degraded.
Hence, there is a need for an apparatus and technique for reducing dielectric absorption in electronic circuits, particularly phase lock loop circuits.